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links: general requirements , specific EEG requirements . sadly, it looks like the IEC wants money for the specification documents.
LVDS Isolator Board:
There is an old (and faulty see issues page) design for an isolator for the headstage lvds/spi connection here which should work pretty well, but needs to be redesigned and tested:
https://github.com/open-ephys/headstage-isolation-board
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