lets use this page to archive some key information on the development of the prototype PCIe board.
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The main issue here is how to implement the intan <> GUI transfer via DMA.
possible options are:
Xilinx DMA example
http://www.xilinx.com/products/intellectual-property/pcie-dma.html
Pros: Example works out of the box?
Cons: ?
Xilybus
Xillybus
Pro: Seems very easy to implement
Cons: closed, licensing likely not compatible with wide adoption
Connectal
https://github.com/cambridgehackers/connectal Looks like a pretty sane
http://www.connectal.org/doc/current/ref/
Pros: License looks very BSD like
Cons: looks like it supports only linux?
OpenCores pcie DMA core
basically a wrapper for the xilinx pcie core providing 2 fifos and a 40mHz control io
http://opencores.org/project,virtex7_pcie_dma,overview
Pros: Open, uses whisbone, looks fairly simple
Cons: only recently got driver (https://github.com/lnls-dig/fpga_pcie_driver), prolly linux only for now
OpenCores PCIe SG DMA controller (scatter gather)
The design implements MAC, Physical (Xilinx Hard and Soft IP Cores) and Transaction Layer (Custom Core) of PCIe.
http://opencores.org/project,pcie_sg_dma (github)
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Pros: comes with driver (linux only)
Cons not tested on kintex architecture, but should be portable pretty easily?
Performance measurements
Measuring round-trip latencies from the open ephys GUI is problematic because of the latencies caused by the processing chain callback and buffer overheads.
For submillisecond feedback it makes more sense to just call the feedback function directly from the data acquisition thread, or in a separate thread that receives data directly from the DMA interface but is not subject to the timing and buffering requirement of the whole processing pipeline.
For testing, Aaron patched a simple threshold detector into the PCIe interface plugin in the Open Ephys GUI, to send a response output whenever the input voltage at the headstage is over a threshold. We ran these tests on a stock 16.04 Ubuntu system with an Intel core i7-3770K @ 3.5GHz.
For input buffer sizes (via Xillybus DMA interface) of 1 sample (33us) we get this:
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