This page is meant as a working document to spec out the requirements and specifications for the next iteration of hardware interfaces for electrophysiology.
see separate page for prototype development and some documentation
see the github repository for all design and source files.
We hope for this project to become not just an open ephys associated standard -
ideally we could end up with a set of open interface standards, code blocks and APIs that many different projects can adapt parts of.
The whitepaper provides a good introduction to the full standard proposal.
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We already defined an API thta that makes switching between interfaces much easier, but this should be resolved asap.
One of the options would be to outsource the development of a driver and firmware - likely expensive and not totally clear on what license we'd get.
Definitely check what the CERN cards use.
Outsource
- Fee for service company, like tier one?
- check if xenomai could do it? Thye already have the RTOS part covered
Existing standards:
EPEE
EPEE is an efficient and flexible host-FPGA PCIe communication library. EPEE suports various generations of Xilinx FPGAs with up to 26.24 Gbps half duplex and 43.02 Gbps fullduplex aggregata throughput in the PCIe Gen X8 mode (tested in Xilinx VC707 evaluation board).
http://cecaraw.pku.edu.cn/Eng_EPEE.html
Riffa
link > Riffa, ( github.)
Pro: cross platform
Cons: ?
Xilybus
http://xillybus.com/
Pro: works already (Aaron's rhythm port)
Cons: closed, licensing likely not compatible with wide adoption
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