This page is meant as a working document to spec out the requirements and specifications for the next iteration of hardware interfaces for electrophysiology.
see separate page for prototype development and some documentation
see the github repository for all design and source files.
We hope for this project to become not just an open ephys associated standard -
ideally we could end up with a set of open interface standards, code blocks and APIs that many different projects can adapt parts of.
The whitepaper provides a good introduction to the full standard proposal.
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EPEE
EPEE is an efficient and flexible host-FPGA PCIe communication library. EPEE suports various generations of Xilinx FPGAs with up to 26.24 Gbps half duplex and 43.02 Gbps fullduplex aggregata throughput in the PCIe Gen X8 mode (tested in Xilinx VC707 evaluation board).
http://cecaraw.pku.edu.cn/Eng_EPEE.html
Riffa
link > Riffa, ( github.)
Pro: cross platform
Cons: ?
XilybusXillybus
http://xillybus.com/
Pro: works already (Aaron's rhythm port)
Cons: closed, licensing likely not compatible with wide adoption
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OpenCores pcie DMA core
basically a wrapper for the xilinx pcie core providing 2 fifos and a 40mHz control io
http://opencores.org/project,virtex7_pcie_dma,overview
Pros: Open, uses whisbonewishbone, looks fairly simple
Cons: only recently got developed a driver (https://github.com/lnls-dig/fpga_pcie_driver), prolly linux probably Linux-only for now
OpenCores PCIe SG DMA controller (scatter gather)
The design implements MAC, Physical (Xilinx Hard and Soft IP Cores) and Transaction Layer (Custom Core) of PCIe.
http://opencores.org/project,pcie_sg_dma (github)
Also see
http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=5782641&filter%3DAND%28p_IS_Number%3A5782103%29%26pageNumber%3D2
Pros: comes with driver (linux only)
Cons not tested on kintex architecture, but should be portable pretty easily?
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