lets use this page to archive some key information on the development of the prototype PCIe board.
The main github repo for this is (for now - we might move this later): https://github.com/open-ephys/next-gen-system
The interface specifications etc are on: PCIe acquisition board (Open Instruments) standard
Also see out slack channel at https://open-ephys.slack.com (email us to get an invite)
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The main issue here is how to implement the intan <> GUI transfer via DMA.
Xillybus see here for specifications
Pro: Seems very easy to implement
Cons: closed, licensing likely not compatible with wide adoption
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For testing, Aaron patched a simple threshold detector into the PCIe interface plugin in the Open Ephys GUI, to send a response output whenever the input voltage at the headstage is over a threshold. We ran these tests on a stock 16.04 Ubuntu system with an Intel core i7-3770K @ 3.5GHz.
For input buffer sizes (via Xillybus DMA interface) of 1 sample (33us) we get this:
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