...
- 0x00: ResetRun (DAC and TTL settings can be ignored)
- 0x02: MaxTimeStepLSb
- 0x04: MaxTimeStepMsb
- 0x06: DataFreqPll (Instead of using the trigger, we can use the write logic of this address to trigger the PLL update. See clock note)
- 0x08: MisoDelay
- 0x0A-0x0E: Unused
- 0x10-0x14: AuxCmdBank1-3
- 0x16-0x1A: AuxCmdLength1-3
- 0x1C-0x20: AuxCmdLoop1-3
- 0x22: Unused
- 0x24: DataStreamSel1234
- 0x26: DataStreamSel5678
(The three following registers have been moved, using what were addresses for dac registers) - 0x28: DataStreamSel9ABC
- 0x2A: DataStreamSelDEF10
- 0x2C: DataStreamEn0x2C
- 0x2E: AuxOutput: A new register. Bits 0-3 control the binary output of the three generic SMAs
- 0x30-0x3C: Unused
- 0x3E: Start Trigger (writing in the bit 0 on this address will not write to any register but trigger acquisition start)
...
Since the Kintex-7 uses different clock generation primitives, a new table for dynamic generation of the data clock is needed. The Kintex-7 PLL features a double divider, with a output of Fout = Fin x M / (O x D). Since the KC705 board features a fixed 200MHz clock, the conversion table is as below.
The DataFreqPll signal must be modified. It ends as follows:
- DataFreqPll[7:0] Value of the D parameter
- DataFreqPll[14:8] Value of the M parameter
- DataFreqPll[15]: '1' means the O parameter is 8, '0' means it's 4
M | O | D | dataclk | Sampling rate | Sampling period |
7 | 125 | 4 | 2,80 MHz | 1,00 kS/s | 1000,0 usec |
7 | 100 | 4 | 3,50 MHz | 1,25 kS/s | 800,0 usec |
21 | 125 | 8 | 4,20 MHz | 1,50 kS/s | 666,7 usec |
14 | 125 | 4 | 5,60 MHz | 2,00 kS/s | 500,0 usec |
35 | 125 | 8 | 7,00 MHz | 2,50 kS/s | 400,0 usec |
21 | 125 | 4 | 8,40 MHz | 3,00 kS/s | 333,3 usec |
14 | 75 | 4 | 9,33 MHz | 3,33 kS/s | 300,0 usec |
28 | 125 | 4 | 11,20 MHz | 4,00 kS/s | 250,0 usec |
7 | 25 | 4 | 14,00 MHz | 5,00 kS/s | 200,0 usec |
7 | 20 | 4 | 17,50 MHz | 6,25 kS/s | 160,0 usec |
56 | 125 | 4 | 22,40 MHz | 8,00 kS/s | 125,0 usec |
14 | 25 | 4 | 28,00 MHz | 10,00 kS/s | 100,0 usec |
7 | 10 | 4 | 35,00 MHz | 12,50 kS/s | 80,0 usec |
21 | 25 | 4 | 42,00 MHz | 15,00 kS/s | 66,7 usec |
28 | 25 | 4 | 56,00 MHz | 20,00 kS/s | 50,0 usec |
35 | 25 | 4 | 70,00 MHz | 25,00 kS/s | 40,0 usec |
42 | 25 | 4 | 84,00 MHz | 30,00 kS/s | 33,3 usec |
28 | 15 | 4 | 93,33 MHz | 33,33 kS/s | 30,0 usec |
56 | 25 | 4 | 112,00 MHz | 40,00 kS/s | 25,0 usec |
14 | 5 | 4 | 140,00 MHz | 50,00 kS/s | 20,0 usec |
Status LEDs
The firmware uses some of the KC705 Evaluation board leds as status indicators:
- LEDs 0-3 are Xillybus indicators. LED 0 should blink to indicate the system's correct operation while LEDs 1-3 are indicators of PCIe transfer
- LED4 is currently unused
- LED5 indicates an overflow of the transmission FIFO. This happens if the system generates data faster than the software can consume. The FIFO will not allow more data until acquisition has reset to avoid block corruption.
- LED6 indicates that the acquisition state machine is working and acquiring data from the headstages.
- LED7 indicates the reset status of the acquisition machine. Should be ON unless the device is open by the GUI.