Possible projects & Future development

This is a list of possible engineering projects using open-ephys or associated standards.
Ideally, we'd like to collect ideas for things that are both technically feasible and interesting for engineering students, and scientifically useful for neuroscientists.

If you have an idea for a project, add it here!
Also, check the issue tracker for feature request, some smaller projects are listed there as well.

Make use of the LEDs to display useful information
(simple verilog)
see here Rhythm firmware fork for how to display things on the LEDs

Expansion board for current aq. board for 1024 channels
(PCB design, verilog, software development)

You can currently only connect two RHD headstages per port, using a Y-adapter, because there's only 2 miso pairs per connector. This gives you 8 RHD chips total, for up to 512 channels (with usb3 and 8x64 ch chips).
We have a few free pins left on the fpga that we pulled out to a .1" header for future expansions so with a few cmos<>lvds bridges (because we dont have enough pins for straight lvds - and this is assuming that the bandwidth of these is not destroyed by the board layout etc) we can theoretically throw in a 2nd row of 4 ports, which would get us to 1024 chs per board. Of course this would require some firmware, api, and GUI updates, and i'm not 100% sure how close this would come to saturating the usb3, though it should fit in theory ( http://www.wolframalpha.com/input/?i=2+byte+*+30kHz+*+1024+*+2+in+MB%2Fs ).

I started putting together an extension board in the https://github.com/open-ephys/acquisition-board repository, if someone is up for some firmware coding this could be a fun project.

Low latency spike detection and sorting
(FPGA, DSP development)

There is some interest in the neuroscience community for closed-loop experiments in which a stimulus is delivered immediately whenever a specific neuron is spiking.
This requires very fast (<1ms) detection of a spike. This will likely require implementing the spike detection and some simple for of spike sorting on the FPGA.

Making use of accelerometer data on freely behaving animals
(Host PC side data processing & analysis)

Many experiments in neuroscience require to assess the behavioural state an animal is in, such as whether it is sleeping or awake, highly active or resting.

Many open-ephys compatible headstages include a 3 axis accelerometer. Currently this data is recorded but not yet used or even pre-processed. It might be possible to extract a lot of useful information form this data that is otherwise only accessible to researchers through methods such as videography, and even simple steps such as a better visualization of the data could help researchers. There might even already be datasets of accelerometer data for which the behavioural state is known.

Implementing simple DSP on the acquisition board FPGA
(FPGA, DSP development)
It could be useful to implement a soft microprocessor on the acquisition board FPGA, in order to enable scientists to run simple closed-loop applications with very little delay directly on the fpga.
The main challenges for this seem to be:

Many application will likely require a pretty feature rich microprocessor with some DSP features.
Ideally, coding for this system should be as simple as coding for an arduino.

Developing an RTXI compatible acquisition board
(PCIe card design, driver development, Real time linux)
-> see also pcie aq board.
The RTXI project (http://www.rtxi.org/) is a standardized architecture for performing fast closed-loop experiments using real time Linux.
Developing a open-ephys compatible acquisition board that works well with RTXI would bridge the existing community of RTXI users that work with intracellular data with the community of users of extracellular recordings.
This would probably yield the most powerful and yet easy to work with system for running complex closed-loop experiments.

Integrate Intan chips onto silicon probes

As channel counts go up, the connection between electrode array and headstage will become a real limitation, in terms of space, weight and cost. I wonder if it would be possible to solder the Intan chips directly to the silicon probes. In that way, two connectors could be eliminated and the electrodes would only need the slim serial connection whatever the channel count.